采用內(nèi)部取樣和保持電路以及差分輸入,使輸入幅度能達到基準電壓的兩倍,廣泛應用在無線基站接收機,多載波多模式接收機,雷達系統(tǒng),通信基礎設備以及功率放大器的線性化.本文提供了ADC12C170的方框圖,以及詳細的應用電路圖和所用材料清單(BOM).
National Semiconductor’s New 12-Bit ADCs for WiMAX Provide the Industry’s Highest SFDR of 84.1 dB at 250 MHz Input Frequency
The ADC12C170 is a high-performance CMOS analog-to digital converter capable of converting analog input signals into 12-Bit digital words at rates up to 170 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample- and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full power bandwidth of 1.1 GHz. The ADC12C170 operates from dual +3.3V and +1.8V power supplies and consumes 715 mW of power at 170 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A powerdown feature reduces the power consumption to 5 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.
The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC12C170 can be operated with an external reference.
Clock mode (differential versus single-ended) and output data format (offset binary versus 2s complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.
The ADC12C170 is pin compatible with the ADC14155, ADC11C125 and ADC11C170.
It is available in a 48-lead LLP package and operates over the industrial temperature range of 40°C to +85°C.
主要特性:
■ 1.1 GHz Full Power Bandwidth
■ Internal sample-and-hold circuit
■ Low power consumption
■ Internal precision 1.0V reference
■ Single-ended or Differential clock modes
■ Clock Duty Cycle Stabilizer
■ Dual +3.3V and +1.8V supply operation
■ Power-down and Sleep modes
■ Offset binary or 2s complement output data format
■ Pin-compatible: ADC14155, ADC11C125, ADC11C170
■ 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)
主要指標:
■ Resolution 12 Bits
■ Conversion Rate 170 MSPS
■ SNR (fIN = 70 MHz) 67.2 dBFS (typ)
■ SFDR (fIN = 70 MHz) 85.4 dBFS (typ)
■ ENOB (fIN = 70 MHz) 10.8 bits (typ)
■ Full Power Bandwidth 1.1 GHz (typ)
■ Power Consumption 715 mW (typ)
應用范圍:
■ High IF Sampling Receivers
■ Wireless Base Station Receivers
■ Power Amplifier Linearization
■ Multi-carrier, Multi-mode Receivers
■ Test and Measurement Equipment
■ Communications Instrumentation
■ Radar Systems
圖1.ADC12C170方框圖:
圖2.采用變壓器驅(qū)動的應用電路圖
圖3. ADC12C170LFEB模擬輸入網(wǎng)絡(FIN < 150 MHz)
圖4.ADC12C170評估板外形圖.
圖5.信號電路圖:
圖6.電源分布圖:
下表為所用材料清單(BOM):
ADC12C170數(shù)據(jù)表:
http://cache.national.com/ds/DC/ADC12C170.pdf
或
http://www.national.com/appinfo/adc/files/ADC12C170MAN.pdf