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      NS低抖動LVDS FPGA接口方案

      更新時間: 2008-06-02 09:16:56來源: 粵嵌教育瀏覽量:1348

        NS公司的DS32EL0421/ DS32ELX0421是低抖動LVDS 并串轉換芯片,而DS32EL0124/DS32ELX0124則是串并轉換芯片.這種SERDES芯片組具有高達5個并行輸入的LVDS通路,數據速率高達3.125Gbps,而在3.125Gbps時的本征抖動為35ps. SERDES芯片組廣泛應用在圖像和顯示器,視頻傳輸,通信系統,測試和測量設備以及工業總線.本文介紹了SERDES芯片組的主要特性,關鍵的指標,典型應用以及典型的接口電路.

        The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
        The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.
        The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion
        DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.
        The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
        The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.
      主要特性:
      ■ 5-bit LVDS parallel data interface
      ■ Programmable transmit de-emphasis
      ■ Configurable output levels (VOD)
      ■ Selectable DC-balanced encoder
      ■ Selectable data scrambler
      ■ Remote Sense for automatic detection and negotiation of link status
      ■ On chip LC VCOs
      ■ Redundant serial output (ELX device only)
      ■ Data valid signaling to assist with synchronization of multiple receivers
      ■ Supports AC- and DC-coupled signaling
      ■ Integrated CML and LVDS terminations
      ■ Configurable PLL loop bandwidth
      ■ Programmable output termination (50Ω or 75Ω).
      ■ Built-in test pattern generator
      ■ Loss of lock and error reporting
      ■ Configurable via SMBus
      ■ 48-pin LLP package with exposed DAP



      關鍵的指標:
      ■ 1.25 to 3.125 Gbps serial data rate
      ■ 125 to 312.5 MHz DDR parallel clock
      ■ -40° to +85°C temperature range
      ■ >8 kV ESD (HBM) protection
      ■ Low Intrinsic Jitter — 35ps at 3.125 Gbps
      目標應用:
      ■ Imaging: Industrial, Medical Security, Printers
      ■ Displays: LED walls, Commercial
      ■ Video Transport
      ■ Communication Systems
      ■ Test and Measurement
      ■ Industrial Bus
               


                          圖1.典型應用

              

                      圖2. DS32ELX0421典型的接口電路

      詳情請見:

      >http://cache.national.com/ds/DS/DS32EL0421.pdf

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