Cypress公司的CYP(V)15G0101DXB單路HOTLink II收發器是點對點通信解決方案，能在高速串行連接如光纖，平衡和不平衡銅傳輸線中傳輸高速信號，信號速率在195 到1500 MBaud。

       發送通路能接受輸入寄存器中的并行字符，進行編碼幷轉換成串行數據，而接收通路則接受串行數據，轉換成并行數據，幷把數據譯碼成字符。本文介紹了 CYP(V)15G0101DXB評估板的主要性能，收發電路方框圖以及評估板的詳細電路圖和所用材料清單（BOM）.

       The CYP(V)15G0101DXB[1] single-channel HOTLink II™ transceiver is a point-to-point communications building block allowing the transfer of data over a high-speed serial link
(optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud.
The transmit channel accepts parallel characters in an Input Register, encodes each character for transport, and converts it to serial data. The receive channel accepts serial data and converts it to parallel data, frames the data to character boundaries, decodes the framed characters into data and special characters, and presents these characters to an Output Register. Figure 1 illustrates typical connections between independent host systems and corresponding CYP(V)(W)15G0101DXB parts. As a second-generation
HOTLink device, the CYP(V)(W)15G0101DXB extends the HOTLink II family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data, command, and BIST) with other HOTLink devices.

The CYV15G0101DXB satisfies the SMPTE 259M and SMPTE 292M compliance as per the EG34-1999 Pathological Test Requirements. The transmit (TX) section of the
CYP(V)(W)15G0101DXB single-channel HOTLink II consists of a byte-wide channel. The channel can accept either eight-bit data characters or pre-encoded 10-bit transmission characters. Data characters are passed from the Transmit Input Register to an embedded 8B/10B Encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual Positive ECL (PECL)-compatible differential transmission-line drivers at a bit-rate of either 10 or 20 times the input reference clock.
The receive (RX) section of the CYP(V)(W)15G0101DXB Single-channel HOTLink II consists of a byte-wide channel. The channel accepts a serial bit-stream from one of two
PECL-compatible differential Line Receivers and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The recovered bit-stream is deserialized and framed into characters, 8B/10B decoded, and checked for transmission errors. Recovered decoded characters are then written to an internal Elasticity Buffer, and presented to the destination host system. The integrated 8B/10B Encoder/Decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface.

The parallel I/O interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. In addition to clocking the transmit path interfaces from one or multiple sources, the receive interface may be configured to present data relative to a recovered clock or to a local reference clock.
The transmit and the receive channels contain BIST pattern generators and checkers, respectively. This BIST hardware allows at-speed testing of the high-speed serial data paths in both transmit and receive sections, as well as across the interconnecting links.
HOTLink II devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-to-point serial links. Some applications include interconnecting backplanes on switches, routers, base-stations, servers and video transmission systems.

主要特性：
Features
Second-generation HOTLink® technology
Compliant to multiple standards
—ESCON®, DVB-ASI, Fibre Channel and Gigabit Ethernet (IEEE802.3z)
—CPRI™ compliant
—CYW15G0101DXB compliant to OBSAI-RP3
—CYV15G0101DXB compliant to SMPTE 259M and SMPTE 292M
—8B/10B encoded or 10-bit unencoded data
Single-channel transceiver operates from 195 to 1500 MBaud serial data rate
—CYW15G0101DXB operates from 195 to 1540 MBaud
Selectable parity check/generate
Selectable input clocking options
Selectable output clocking options
MultiFrame™ Receive Framer
—Bit and Byte alignment
—Comma or full K28.5 detect
—Single- or Multi-Byte framer for byte alignment
—Low-latency option
Synchronous LVTTL parallel input and parallel output interface
Internal phase-locked loops (PLLs) with no external PLL components
Dual differential PECL-compatible serial inputs
—Internal DC-restoration
Dual differential PECL-compatible serial outputs
—Source matched for driving 50Ω transmission lines
—No external bias resistors required
—Signaling-rate controlled edge-rates
Optional Elasticity Buffer in Receive Path
Optional Phase Align Buffer in Transmit Path
Compatible with
—Fiber-optic modules
—Copper cables
—Circuit board traces
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Per-channel Link Quality Indicator
—Analog signal detect
—Digital signal detect
Low power 1.25W @ 3.3V typical
Single 3.3V supply
100-ball BGA
Pb-Free package option available
0.25μ BiCMOS technology


圖1.HOTLink II 系統連接圖



圖2. CYP15G0101DXB邏輯方框圖

The CYP15G0101DXB single-channel HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.
This document describes the operation and interface of the CYP15G0101DXB evaluation board. The evaluation board allows users to become familiar with the functionality of the CYP15G0101DXB.



圖3. CYP15G0101DXB評估板外形圖

Kit Contents
CYP15G0101DXB evaluation board (CYP15G0101DXB-EVAL)
Dear Customer letter
a CD containing
— CYP15G0101DXB data sheet
— CYP15G0101DXB-EVAL user’s guide
— HOTLink II application notes
— BSDL model
— CYP15G0101_EVAL.PDA.



圖4. CYP15G0101DXB 發送部分方框圖



圖5. CYP15G0101DXB 接收部分方框圖
下面是 CYP15G0101DXB 評估板電路圖



圖6.  CYP15G0101DXB-EVAL 評估板電路圖



圖7.  CYP15G0101DXB-EVAL 評估板發送和接收電路圖



圖8.  CYP15G0101DXB-EVAL 評估板控制信號電路圖



圖9.  CYP15G0101DXB-EVAL 評估板發送和接收時鐘電路圖



圖10.  CYP15G0101DXB-EVAL 輸入電源電路圖
下表是CYP15G0101DXB-EVAL 評估板所需材料清單(BOM)